Map of content for computer architecture — the design of programmable digital systems. From the abstract instruction set the programmer sees, down through processor internals, memory hierarchy, I/O, and the software toolchain that bridges high-level code to executable bits.
Foundations
What computer architecture is and how it differs from organization.
- Computer architecture vs computer organization — the abstraction line.
- Computer types — embedded, personal, server, supercomputer, cloud.
- Functional Units of a Computer — the five-unit model.
- Basic Operational Concepts — fetch, decode, execute, repeat.
- Computer performance — what makes programs run faster: technology, parallelism, ISA choices.
Instruction set architecture
The programmer’s view of the machine.
- Instruction Set Architecture — what an ISA defines, RISC vs CISC.
- Register transfer notation — precise notation for instruction behavior.
- Addressing modes — how operands are computed.
- Straight-line sequencing — default execution flow.
Nios II as a worked example
A specific RISC ISA used as the running example.
- Nios II assembly language — overview.
- Nios II data-movement instructions — mov, ldw, stw.
- Nios II arithmetic instructions — add, sub.
- Nios II branch instructions — conditional and unconditional control flow.
- Subroutine design process — top-down from problem to assembly.
Processor internals
The hardware that runs instructions.
- Program counter (PC) — address of next instruction.
- Instruction register (IR) — currently executing instruction.
- General-purpose registers — the fast storage at the top of the hierarchy.
- Hardware datapath — the circuits that move data.
- Control unit and control signals — the timing logic that drives the datapath.
- Instruction execution cycle — the five-step fetch/decode/execute/memory/writeback cycle.
- Memory Read and Write Operations — the processor-memory interface.
Memory model
How the processor sees and addresses memory.
- Memory address — the linear address space.
- Byte addressability — addressing individual bytes.
- Endianness — big-endian vs little-endian.
- Word alignment — the speed/correctness trade-off.
Stack and subroutines
How function calls work in hardware.
- Stack (computing) — LIFO memory region (also a data structure).
- Stack frame — per-call portion of the stack.
- Subroutine — function call mechanics.
- Link register — where return addresses live.
- Subroutine linkage — the calling convention.
- Subroutine nesting — handling nested calls.
Memory system
The hierarchy from registers to disk.
- Memory hierarchy — registers, cache, RAM, SSD, disk, plus tape and network for the lowest tiers.
- Random-access memory — RAM as a category.
- Memory cell — the bit storage primitive.
- Static RAM (SRAM) — fast but expensive.
- Dynamic RAM (DRAM) — slower but dense.
- Synchronous DRAM (SDRAM) — clocked DRAM with burst transfers.
- Read-only memory (ROM) — non-volatile, programmed at fab time.
- EEPROM and flash memory — electrically reprogrammable non-volatile.
- Memory controller — manages the DRAM interface.
Cache
Bridging the speed gap.
- Cache memory — overview, multiple levels.
- Cache locality — temporal and spatial.
- Cache address mapping — tag, index, offset bits.
Virtual memory
Apparent memory beyond physical RAM.
- Virtual memory — page-based abstraction.
- Translation lookaside buffer — the address-translation cache.
I/O
Communicating with the outside world.
- I-O device interface — DATA, STATUS, CONTROL registers.
- Program-controlled I-O — polling.
- Interrupt-based I-O — event-driven.
- Interrupt service routine — the handler.
- Processor Status (PS) register — the IE bit and friends.
- Interrupt vector table — mapping interrupts to handlers.
Software toolchain
From source code to running program.
- Compiler — high-level language to assembly.
- Assembler — assembly to machine code.
- Two-pass assembler — handling forward references.
- Linker — combining object files into executables.
- Loader — getting executables into memory.
- Object file — intermediate format.
This MOC builds on Digital logic (which provides the gates, registers, and FSMs that physically implement processors). It connects to Data structures for the in-memory layout of program data and to Differential equations for the analog circuit behavior of memory cells (RC time constants, propagation delays).