Static RAM (SRAM) is a volatile memory technology that uses a 6-transistor flip-flop per cell. Each cell holds its bit indefinitely as long as power is supplied — no refresh needed, hence “static.”
SRAM is the fast, expensive end of the Memory hierarchy. Used for processor registers, on-chip cache (L1, L2, L3), and high-speed external memories where speed matters more than cost.
Properties
- Cell: 6 transistors arranged as a cross-coupled pair of inverters with two access transistors.
- Speed: ~ to ns access.
- Density: low (compared to DRAM). 6 transistors per bit limits how many bits you can pack on a chip.
- Cost per bit: high.
- Volatile: data is lost when power goes off.
- No refresh needed: the cell holds its state indefinitely as long as Vdd is supplied.
Why 6 transistors
A pair of cross-coupled inverters forms a bistable element — two stable states (Q = 0 or Q = 1), and external “noise” smaller than half the supply can’t flip it. Each inverter is 2 transistors (an NMOS and PMOS in CMOS), so the storage core is 4 transistors. Add 2 more transistors as access switches that connect the cell to the bit lines during read or write.
Total: 6 transistors per bit.
The bistable design is what makes SRAM fast (no waiting for a capacitor to charge or discharge) and immune to leakage (the cross-coupled inverters actively drive the bit lines).
Address pin count
SRAM chips have one address pin per address bit — the entire address is provided to the chip simultaneously. This contrasts with DRAM, which multiplexes addresses in two halves to save pins.
For a SRAM chip ( bytes), 17 address pins. Plus 8 data pins, plus power, ground, chip select, output enable, write enable. Reasonable pin count for the simpler RISC bus designs.
The non-multiplexed addressing keeps SRAM simpler to use — no row/column timing protocols to follow, no refresh controller needed.
Worked example: 128K × 8 SRAM organization
Capacity: bits KB.
Memory cell array: physically arranged as a array of cells (1 Mbit total).
Of the 17 address bits:
- Upper 10 bits → decode to one of rows.
- Lower 7 bits → select one of groups of 8 cells within the row.
So each row holds bits, matching the column count. One row contains the data for 128 consecutive byte-addressable locations.
Use cases
SRAM is everywhere speed matters more than capacity:
- Processor registers — the absolute fastest tier. Architectural register files are usually built from multi-ported SRAM cells (8T, 10T, or more), not the standard 6T cell described above. The extra transistors give the cell several independent read or write ports so multiple instructions can read/write registers in the same cycle. The 6T cell is single-ported and would bottleneck a wide superscalar pipeline.
- L1, L2, L3 caches — on-chip SRAM, with hit times from ns (L1) to ns (L3).
- TLBs — small SRAM tables for fast address translation. See Translation lookaside buffer.
- External SRAM — used in embedded systems for fast scratch memory, in network routers for packet buffers, in old game consoles for video memory.
For bulk storage you’d never use SRAM — too expensive per bit, too power-hungry, and too low-density. That’s where DRAM takes over.