Dynamic RAM (DRAM) is a volatile memory that uses just 1 transistor + 1 capacitor per cell. The capacitor stores the bit’s value as charge. The single-transistor design is dramatically denser (and cheaper per bit) than SRAM, but the capacitor leaks — cells have to be refreshed every few milliseconds or they lose their data.
DRAM is the standard for main memory in computers. Today’s RAM modules are almost universally DRAM.
Properties
- Cell: 1 transistor + 1 capacitor.
- Speed: ~ to ns access (slower than SRAM by ~10×).
- Density: very high. A single DRAM chip holds gigabits.
- Cost per bit: low.
- Volatile: data lost on power-off.
- Requires refresh: every cell must be read and rewritten periodically (typical: every 64 ms).
Why 1 transistor
The cell is one access transistor gating one tiny capacitor. To write: drive the bit line, turn on the transistor, the capacitor takes the bit-line’s charge or discharge. To read: turn on the transistor, the capacitor’s small charge appears on the bit line, a sense amplifier detects whether it’s or .
The minimal cell count is what gives DRAM its density. Compare to SRAM’s 6 transistors per bit. Per-cell area, DRAM is roughly 15–25× denser: a DRAM cell is around – where is the process feature size, while a 6T SRAM cell is roughly –. Account for sense amplifiers, decoders, and other peripheral overhead and the system-level density advantage shrinks to about 8–15× — still much larger than the “6×” you’d get from naively comparing transistor counts.
The refresh problem
The capacitor isn’t perfect — charge leaks out gradually through the access transistor and substrate. After a few milliseconds, the cell can’t be reliably distinguished from .
So DRAM chips include a refresh controller that periodically reads each row (which automatically restores the cell’s value through the sense amplifier) and rewrites it. This typically happens every ms. Refresh consumes some bandwidth — the chip is busy refreshing instead of serving reads — but it’s necessary.
Refresh is hidden from the processor by the memory controller; software doesn’t have to know.
Multiplexed addressing
DRAM chips have multiplexed address pins: instead of providing all address bits simultaneously, the chip accepts the address in two halves (row half, then column half) on the same pins. A signal called RAS (row address strobe) latches the row address; another, CAS (column address strobe), latches the column address.
This halves the pin count of the chip package — a big deal for chips with 30+ address bits where dedicating a pin per bit would balloon the package.
The protocol adds latency (you have to send the address in two steps), so DRAM tends to be slower per access than SRAM, on top of the inherent slowness of charging and sensing the small storage capacitor (the time it takes the capacitor’s tiny charge to develop a detectable voltage on the bit line, which the sense amp then has to amplify).
Synchronous variant
The original DRAM was asynchronous — the external memory controller drove every step explicitly. Modern DRAM is almost universally SDRAM, which adds a clock input and supports high-bandwidth burst transfers. SDRAM further evolved into DDR (Double Data Rate, transferring on both clock edges), DDR2, DDR3, DDR4, DDR5 — each generation faster and more power-efficient.
Memory controller
A memory controller sits between the processor and the DRAM chips, handling:
- Refresh scheduling.
- Row/column address multiplexing.
- Bank scheduling (modern DRAMs have multiple banks for parallelism).
- Decoding high-order address bits to assert the right Chip Select signal for the correct module (when there are multiple DRAM modules).
- Burst transfers.
Modern processors integrate the memory controller on-chip for lower latency. It used to be a separate chip on the motherboard’s “northbridge.”
DRAM in the hierarchy
DRAM is the workhorse of main memory. Above it (faster, smaller): SRAM caches and registers. Below (slower, larger): SSDs, hard disks. The factor-of-10 speed gap between DRAM and processor caches is what makes the cache so important — without caches, the CPU would spend most of its time waiting on DRAM.