Register transfer notation

Register transfer notation (RTN) is a precise, hardware-oriented way to describe what an instruction does. It uses arrows for assignment and brackets for “contents of” — an unambiguous shorthand for the data movement and computation a processor performs.

The conventions:

• $\leftarrow$ means “is assigned” (transfer of value).
• $[X]$ means “the contents of location $X$” — distinguishes a register/memory address from its value.

So:

$R2\leftarrow [\text{LOC}]$

reads as “R2 is assigned the contents of memory location LOC.” The memory location LOC isn’t moved into R2 — its contents are.

Without the brackets, you’d be transferring the address itself:

$R2\leftarrow \text{LOC}$

This loads the address of LOC into R2 (analogous to movia in Nios II). The brackets matter.

Composing operations

Multi-step expressions chain naturally:

$R4\leftarrow [R2]+[R3]$

Read R2 and R3, add, store the sum in R4.

$R5\leftarrow [[R2]]$

Outer brackets are around the inner expression $[R2]$, so this means “use the contents of R2 as a memory address, then load the contents at that address.” A single-step pointer dereference.

RTN for an instruction’s behavior

Every instruction in an ISA can be described in RTN. For example, Load R2, A:

$R2\leftarrow [A]$

For Add R4, R2, R3:

$R4\leftarrow [R2]+[R3]$

For Store R4, A:

$[A]\leftarrow [R4]$

(Note: the LHS has brackets — we’re modifying the contents of memory location A, not the address.)

RTN for the datapath

RTN is also used to describe the per-cycle behavior of a pipelined processor. For Nios II’s 5-stage pipeline:

Instruction type	Step 3 (Execute)	Step 4 (Memory)	Step 5 (Writeback)
ALU	$RZ\leftarrow [RA]\text{ op }[RB]$	$RY\leftarrow [RZ]$	$Rd\leftarrow [RY]$
Load	$RZ\leftarrow [RA]+X$	$RY\leftarrow [[RZ]]$	$Rt\leftarrow [RY]$
Store	$RZ\leftarrow [RA]+X$; $RM\leftarrow [RB]$	$[RZ]\leftarrow [RM]$	(no action)
Call	$\text{PC\_Temp}\leftarrow [PC]$; $PC\leftarrow \text{address}$	$RY\leftarrow [PC\_Temp]$	$\text{LINK}\leftarrow [RY]$
Return	$PC\leftarrow [RA]$	(no action)	(no action)

Each row spells out exactly which inter-stage register holds what at each cycle. RA, RB, RZ, RY, RM are the inter-stage registers (see Hardware datapath).

Why use RTN

Three reasons over plain English:

1. Unambiguous. “Load R2 from LOC” can mean two things; $R2\leftarrow [\text{LOC}]$ can only mean one.
2. Implementation-oriented. RTN maps directly to the wires and registers in the datapath. You can read an RTN expression and know which signals to assert.
3. Composable. Sequences of RTN steps describe a multi-cycle instruction or an ISA in detail. Easy to reason about and verify.

It’s the standard notation in Computer Architecture and most computer architecture textbooks. Slightly different conventions exist (some use M[X] instead of [X] for memory contents) but the idea is the same.