Program counter

The program counter (PC) is the processor register that holds the address of the next instruction to be fetched. Every cycle the processor uses the PC to know where to read the next instruction from memory; after each fetch, the PC is incremented (or modified by a branch) so it points to the next instruction.

In a 32-bit RISC machine, instructions are 4 bytes wide and PC is incremented by 4 per cycle during straight-line execution. After fetching the instruction at address $i$, PC becomes $i+4$.

The PC is part of the datapath — it’s a register, with an enable input and a load input — but it’s controlled by the control unit which decides when and how it changes.

When PC changes

Three ways:

1. Sequential (the common case): $\text{PC}\leftarrow \text{PC}+4$. After every normal fetch.
2. Branch / jump: $\text{PC}\leftarrow \text{branch target}$. The branch target is either a label resolved at assembly time (relative to current PC + offset) or an address computed from a register.
3. Subroutine call / return: $\text{PC}\leftarrow \text{call target}$ on call; $\text{PC}\leftarrow \text{[link register]}$ on return.

Any update to PC happens through a multiplexer (called MuxPC in the datapath) that picks among PC+4, branch offset target, RA-based return target.

What PC is not

• PC is not a control signal — it doesn’t tell the processor what to do, just where to look for the next instruction.
• PC does not hold the instruction itself — that’s the IR.
• PC is updated only when enabled by the control unit. It’s not a free-running counter.

Saving PC for subroutines and interrupts

When a subroutine is called, the processor needs to remember where to return to. The address of the instruction after the call is saved (typically into the link register or onto the stack) and PC is set to the subroutine’s entry point. On return, PC is restored from the saved address.

Same mechanism for interrupts: PC is saved (along with other state) so the interrupted program can resume after the ISR completes.

In the datapath

PC sits in the instruction address generator along with helper components like PC-Temp (used to hold the saved PC during call instructions) and an adder for computing PC + 4 or PC + branch offset.

The MuxPC selects among:

• PC + 4 (or PC + offset for branches), via the adder
• RA from the register file (for return-from-subroutine)

The result feeds back into PC for the next cycle. See Hardware datapath for the full picture.