The control unit is the part of the processor that generates the signals telling the rest of the hardware what to do at each clock cycle. It looks at the IR and the current stage of the cycle, and drives the control signals that enable register writes, select multiplexer paths, assert memory operations, and so on.
The Hardware datapath is the circuits that move data; the control unit is the logic that tells those circuits when and how. Together they’re the processor.
What the control signals look like
Each cycle is divided into named stages (T1 = Fetch, T2 = Decode, T3 = Execute, T4 = Memory, T5 = Writeback). Control signals are typically expressed as Boolean equations of stage signals (T1..T5) and instruction-type signals (ALU, Load, Store, Branch, Call, etc.).
Some examples:
RF_Write (register file write enable)
You only write to the register file in stage 5, and only for instructions that produce a result destined for a register:
Stores don’t write the register file. Branches don’t either. Only ALU operations, Loads, and Calls (which write the link register) trigger a register write in stage 5.
Mem_Read (memory read enable)
You read memory during Fetch and during the Memory stage of a Load:
Stores write memory; ALU operations don’t touch memory at all.
IR_en (instruction register enable)
The IR is updated only during Fetch when the memory transfer completes. MFC (“memory function complete”) is a signal from the memory subsystem that says “data is valid on the bus”:
PC_en (program counter enable)
PC updates after a fetch (T1) or after a branch/jump in stage 3:
The first term increments PC by 4 after a successful fetch; the second term loads PC with a branch target if the instruction is a taken branch.
Form of the control unit
In a simple design, the control unit is a piece of combinational logic — a truth table mapping (instruction type, stage) → (control signals). For RISC machines with simple, regular instruction encoding, this works well.
For more complex CISC machines, control is often implemented as a microcoded ROM — each instruction is a sequence of micro-instructions, each holding the control signals for one cycle. This trades a bit of speed for flexibility (changing a micro-instruction is easier than redesigning gates).
Modern high-end CPUs use a mix: most simple instructions are hard-wired for speed; complex instructions trigger microcode sequences.
Where the signals go
Each control signal goes to a specific point in the Hardware datapath:
RF_Write→ register file’s write-enable pin.Mem_Read,Mem_Write→ memory interface.IR_en→ IR’s load-enable.PC_en→ PC’s load-enable.MuxPC select,MuxY select,MuxB select,MuxMA select→ mux select inputs.ALU op→ ALU’s operation-select inputs.
The control unit produces all these every cycle; the datapath responds.
How the control unit knows what cycle it is
The control unit maintains its own small state machine — typically just a counter or a one-hot encoded “current stage” register. After Fetch (T1) it advances to Decode (T2), then Execute (T3), Memory (T4), Writeback (T5), then back to T1 for the next instruction.
In a pipelined design, multiple stage signals are active simultaneously (different instructions in different stages), so the control logic gets more complex — but the same idea applies.
Worked example
Tracing the control signals for a Load instruction ldw R5, 0(R4):
| Cycle | Stage | Active signals |
|---|---|---|
| 1 | Fetch | Mem_Read, IR_en (after MFC), PC_en |
| 2 | Decode | (read R4 into RA; signals to register file) |
| 3 | Execute | MuxB select = immediate, ALU op = add, latch RZ |
| 4 | Memory | Mem_Read, MuxMA select = data (RZ), latch RY from MuxY |
| 5 | Writeback | RF_Write, register file destination = R5 |
For an ALU operation like add R3, R1, R2, similar but no memory access in stage 4 (just RY ← RZ).
For a Store, similar to Load through stage 3, but stage 4 is Mem_Write and stage 5 is no-op.
This is what “exam questions ask you to write logic equations for control signals” means — you express each signal as a Boolean function of T1..T5 and the instruction-type signals, like the RF_Write formula above.