Memory Read and Write Operations

The processor talks to memory through two basic operations: read (memory → processor) and write (processor → memory). Both go through the processor-memory interface — a block on the processor side that handles addressing, control signals, and the data bus.

For a read, the interface puts the address on the address bus, asserts the Read control line, and waits for memory to drive the requested word onto the data bus. For a write, the interface puts the address on the address bus and the data on the data bus, then asserts Write to make memory store it.

Memory is passive — it just sits there responding to address + control signals. The processor’s control unit decides when reads and writes happen and what address goes out.

Instruction fetch always uses Read

Every instruction starts with a memory read to fetch the instruction itself. The sequence:

1. PC value is sent out as the address.
2. Control unit asserts Read.
3. Memory drives the instruction word onto the data bus.
4. The IR loads from the data bus.
5. Decoding begins on the contents of IR.

Memory has no idea this is an instruction rather than data — it’s just bits on a bus. The processor interprets the bits as an instruction by loading them into IR.

Data read (Load)

For an instruction like Load R1, A (or ldw r1, A in Nios II):

1. Address of A is computed (often base register + offset) and sent on the address bus.
2. Control unit asserts Read.
3. Memory drives the word at that address onto the data bus.
4. The datapath loads it into the destination register.

In a five-stage datapath this happens in stage 4 (Memory). The address itself was computed by the ALU in stage 3 and is now in the inter-stage RZ register.

Data write (Store)

For Store R1, A:

1. Address of A goes on the address bus.
2. Datapath puts the value of R1 on the data bus.
3. Control unit asserts Write.
4. Memory updates the word at that address.

No write-back to a register is needed — the result lives in memory now.

Read vs Write summary

Operation	Initiated by	Data direction	Purpose
Read	Control unit	Memory → datapath	Fetch instruction or data
Write	Control unit	Datapath → memory	Store result or output

Key separation of concerns

A few rules to keep straight:

• Instruction fetch always uses Read. No exceptions.
• PC and IR are datapath registers. They hold values; the control unit decides when to update them.
• The control unit asserts Read/Write. Memory itself doesn’t decide anything.
• Memory is passive. It returns or stores bits when told to.
• Meaning lives in the CPU. Memory doesn’t know if a word is an instruction, an integer, a pointer, or a character — that’s all interpretation by the processor based on which instruction is using the word.

For the cycle in which reads and writes happen relative to other steps, see Instruction execution cycle. For the path the data takes once read into the processor, see Hardware datapath.