A combinational circuit is a digital circuit whose output is a pure function of its current inputs — no memory, no clock, no history. Apply the same inputs and you always get the same output, with a small delay for signal propagation.
The contrast is the sequential circuit, which has internal state and depends on past inputs as well.
Combinational circuits are built entirely from logic gates arranged in a feed-forward network — no feedback loops, no flip-flops, no latches. Examples include adders, multiplexers, decoders, and encoders.
How to recognize one
If you can describe the circuit’s output entirely with a Boolean equation in terms of its inputs, it’s combinational. If the description requires phrases like “previous state,” “after clock edge,” or “if it was set last time,” it’s sequential.
A truth table fully specifies a combinational circuit. (For sequential circuits you need a state table, not a truth table.)
Implementation styles
Combinational circuits can be implemented in many forms — all logically equivalent but with different cost / speed trade-offs:
- Two-level SOP or POS: AND-then-OR or OR-then-AND. Fast (only two gate delays) but high Fan-in for complex functions.
- Multilevel: factored into several levels of smaller gates. Slower per output but smaller and more amenable to LUTs.
- LUT: store the truth table directly. Used by FPGAs.
- PAL: programmable AND/OR planes.
Limits
Pure combinational logic can compute any Boolean function. What it cannot do:
- Remember anything (no state).
- Generate sequences (no time-based behavior).
- Synchronize with a clock (no triggering).
Once any of those is needed, the circuit needs storage elements — and you’ve moved into sequential design. Most real systems are a mix: combinational logic for the “what should the next state be” computation, sequential storage to hold the state between clock edges. See Mealy machine and Moore machine for the standard architectures.
Propagation delay
Even though combinational circuits have no clock, they’re not instantaneous. Each gate takes a finite time to switch — typically 0.1–10 ns for modern CMOS gates. The total propagation delay of a combinational circuit is the longest path (in gates) from any input to any output.
For a 4-bit ripple-carry Adder, the carry must propagate through 4 full-adders before the most significant sum bit is final. Each full-adder might take 2 ns, so the total delay is 8 ns. The output is undefined during this transient — only after the propagation delay can you read a stable result.
This delay limits how fast you can clock a synchronous circuit that includes the combinational block. With pure combinational delay alone, MHz. Setup time, hold time, and clock-to-Q delay of the surrounding flip-flops add to the period, dropping the realistic ceiling closer to 80–100 MHz.
Reducing combinational delay (via Multilevel synthesis, faster gate libraries, parallel structures like carry-lookahead) is a major theme of digital design.
Glitches and hazards
Combinational circuits can produce transient glitches — momentary wrong outputs while signals propagate. Two main causes:
- Static hazard: an input changes in a way that should leave the output unchanged, but the path through one gate arrives faster than another, causing a brief incorrect transition.
- Dynamic hazard: an input change that should cause one output transition causes multiple due to differing path delays.
Glitches don’t matter if the output is sampled by a flip-flop only at clock edges (after settling). They matter if the output drives an asynchronous downstream circuit.
Hazard-free design adds redundant terms (consensus terms in Boolean algebra) to ensure smooth transitions. For most synchronous designs, just letting glitches settle within the clock period is fine.
Standard combinational building blocks
Most digital systems are built by composing standard combinational components:
| Block | Function |
|---|---|
| Adder | Arithmetic addition (and via tricks, subtraction) |
| Multiplexer | Select 1-of-N data sources |
| Demultiplexer | Route 1 input to 1-of-N destinations |
| Decoder | Binary-to-one-hot conversion |
| Encoder | One-hot-to-binary conversion |
| Comparator | Equality and ordering checks |
| Shifter | Bit-shifting (left or right, by fixed or variable amount) |
| ALU | Combination of arithmetic and logic operations under control |
Larger combinational blocks (multipliers, dividers, floating-point units) are built from these primitives, often via multilevel synthesis.
Worked example
A 1-bit comparator that outputs 1 if :
Truth table for inputs :
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The output is 1 only when and . As a Boolean expression: .
That’s a single-gate combinational circuit (one AND with one inverted input) — no feedback, no memory, no clock. Pure function of inputs.
For multi-bit comparison, replicate this pattern with logic to handle all bit positions correctly. The result is still combinational, but the circuit gets bigger as bit width grows.
For the contrast with circuits that do have memory, see Sequential circuit.