Decoder

A decoder converts a binary-encoded input into a one-hot output. With $n$ input bits, it produces $2^n$ output lines, exactly one of which is asserted at any time — the line whose index matches the input value.

So a 2-to-4 decoder takes 2 inputs and 4 outputs: input $00$ asserts $y_0$, input $01$ asserts $y_1$, etc. Output $y_i$ corresponds to minterm $m_i$ — the AND of the input bits in their appropriate complemented/uncomplemented combination.

For $n$ inputs and $2^n$ outputs, each output is a different $n$-input AND of the input lines (and their complements). The whole decoder is essentially a parallel computation of every minterm.

Why this is useful

Three common uses:

1. Address decoding. A processor’s address bus selects one memory location out of many. The decoder takes the address bits and produces a single chip-select line that activates the matching memory chip or register.

2. Function generation. Combine the decoder outputs with an OR gate, and you get any SOP expression directly. The decoder produces all minterms; the OR picks which ones contribute to your function.

3. Used as a Demultiplexer. Adding a data input feeds it through to whichever output the address selects.

Enable input

Decoders typically have an enable input, often labelled $E_n$ (with "$n$" a superscript meaning enable — not ”$E$ subscript $n$” or some bit count $n$). When $E_n=1$, the decoder works normally. When $E_n=0$, all outputs are forced low — the decoder is disabled. Some texts use $E$, $\text{EN}$, or $G$ for the same signal.

This matters for two reasons:

• Building bigger decoders from smaller ones. A 3-to-8 decoder can be built from two 2-to-4 decoders, with the third input bit driving the enables (one decoder enabled when bit 2 is high, the other when bit 2 is low).
• Power and bus management. Disabled decoders don’t drive their outputs, so multiple decoders can share output wires safely (one drives, the others stay quiet).

In the diagram above: when $w_2=0$, the upper decoder’s enable is on (and the lower one’s is off via the inverter), so $y_0..y_3$ behave normally and $y_4..y_7$ stay low. When $w_2=1$, the roles swap.