Multiplexer

A multiplexer (MUX) is a combinational circuit that selects one of several data inputs and routes it to a single output. The choice is made by select inputs.

A 2-to-1 MUX with data inputs $I_0,I_1$, select $S$, and output $f$:

$f=\overline{S}{I}_0+S{I}_1$

When $S=0$, the output is $I_0$; when $S=1$, the output is $I_1$. The select bit picks the lane.

In general, an $n$-to-$1$ MUX needs $\lceil {\log }_{2}n\rceil$ select bits. A 4-to-1 MUX has 2 select bits; an 8-to-1 has 3. The numbers written inside the MUX block diagram correspond to which input is connected when the select inputs hold that value.

Why it matters

Three common roles:

1. Routing. Pick which of several signals goes downstream — bus arbitration, register file outputs, ALU operand selection.
2. Function generation. Hard-code the data inputs to constants or simple combinations of variables, and the MUX implements an arbitrary Boolean function. This is what a LUT is, internally.
3. Encoding Shannon’s expansion theorem. Any function $f(w_1,w_2,\dots ,w_n)$ can be decomposed as $\overline{w_1}f(0,w_2,\dots ,w_n)+w_{1}f(1,w_2,\dots ,w_n)$, which is exactly a 2-to-1 MUX with $w_1$ as select. The two cofactors $f(0,\dots )$ and $f(1,\dots )$ are themselves Boolean functions of the remaining variables — you still have to build them. Larger MUXes implement deeper decompositions: a 4-to-1 MUX with $w_1,w_2$ as select takes the four cofactors $f(0,0,\dots ),f(0,1,\dots ),f(1,0,\dots ),f(1,1,\dots )$ as data. The MUX itself is “free”; the hardware to produce the data inputs is not.

Examples

For a 2-to-1 MUX with select $S$ and inputs $A,B$:

$\text{MUX}(S;A,B)=\overline{S}A+SB$

Composing MUXes builds bigger functions:

${\text{MUX}}_1(x_2;\overline{x_3},x_3)=x_2{x}_3+\overline{x_2}\overline{x_3}=x_2\odot x_3$

${\text{MUX}}_2(x_2;x_3,\overline{x_3})=x_2\overline{x_3}+\overline{x_2}{x}_3=x_2\oplus x_3$

A third MUX can use these as data and $x_1$ as select:

${\text{MUX}}_3(x_1;x_2\oplus x_3,x_2\odot x_3)=x_1\oplus x_2\oplus x_3$

That gives 3-input XOR (parity) from three 2-to-1 MUXes — no XOR gates required.

The reverse circuit, taking a single input and routing it to one of $n$ outputs based on select bits, is a Demultiplexer.