Half-adder

A half-adder adds two single bits and produces a two-bit result: a sum $S$ and a carry-out $C$. It’s the simplest binary addition cell — the building block from which a full-adder and then a multi-bit adder are built.

It’s called half because it doesn’t accept a carry-in from a previous stage. That makes it adequate for adding the least-significant bits of two numbers (where there’s no incoming carry) but useless for any column above bit 0, where the carry from the previous column must also be folded in.

Truth table

There are four input combinations of two bits $A$ and $B$:

$A$	$B$	$S$	$C$
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Reading the table: the sum $S$ is $1$ when exactly one input is $1$, which is the definition of XOR. The carry $C$ is $1$ only when both inputs are $1$, which is plain AND.

Boolean expressions

$S=A\oplus B$

$C=AB$

The XOR captures “an odd number of 1s” — for two inputs that just means exactly one of them is $1$. The AND captures “both 1s” — the only case that overflows a single bit.

Circuit

One XOR gate produces $S$, one AND gate produces $C$. Two gates total. There’s no internal state and no feedback — it’s a combinational circuit in its simplest form.

Limitation

A half-adder ignores any incoming carry. If you tried to wire two half-adders side by side to add two 2-bit numbers $A_1{A}_0+B_1{B}_0$, the carry out of the bit-0 half-adder would have nowhere to go — the bit-1 half-adder doesn’t have a carry-in input. You’d silently lose the carry every time both LSBs are $1$.

The fix is the full-adder, which adds three inputs ($A$, $B$, and $C_{in}$) and so can be cascaded properly. A full-adder can in fact be built from two half-adders plus an OR gate — the half-adder isn’t useless, it’s just incomplete on its own.