Adder

An adder is a digital circuit that performs binary addition. The adder family scales from a single-bit cell up through ripple-carry and carry-lookahead designs that handle arbitrarily wide operands. This note compares the cells and topologies; the per-cell details live in their own notes.

When you add two binary digits $A$ and $B$, the four input combinations $0+0$, $0+1$, $1+0$, $1+1$ produce results that need at most two bits — a sum and a carry. So even the simplest binary add has two output bits. Cascading those one-bit cells, with the carry of each column feeding the next, builds a wide adder.

The two cells

Two basic single-bit adders, distinguished by whether they accept a carry-in:

• A Half-adder adds two bits ($A$, $B$) and produces a sum and carry-out. No carry-in. Useful only for the LSB position; can’t be cascaded.
• A Full-adder adds three bits ($A$, $B$, $C_{in}$) and produces a sum and carry-out. The cascadable cell — every bit position above bit 0 needs one. A full-adder can be built from two half-adders plus an OR gate.

For an $n$-bit adder you usually use $n$ full-adders (or $n-1$ full-adders plus one half-adder for bit 0, a minor optimisation).

Ripple-carry adder

A ripple-carry adder chains $n$ full-adders. The carry-out of stage $i$ becomes the carry-in of stage $i+1$. The first stage’s carry-in is normally $0$ — or $1$ if you’re using the 2’s complement subtraction trick (see below).

The design is easy to lay out — every stage is identical, neighbours-only wiring, scales to any width. The downside is latency: the carry has to ripple through every stage before the final answer is valid. For a 32-bit adder, that’s 32 full-adder delays in the worst case.

Fine for low speeds. Slow for wide adders at high clock rates.

Carry-lookahead adder

A carry-lookahead adder (CLA) computes every carry directly from the inputs, in parallel, by decomposing per-bit behaviour into generate ($G_i=A_i{B}_i$) and propagate ($P_i=A_i\oplus B_i$) signals and flattening the recurrence $C_{i+1}=G_i+P_i{C}_i$. The carry chain becomes $O(\log n)$ deep with hierarchical group lookahead, at the cost of more silicon than ripple-carry. See Carry-lookahead adder for the full derivation, the group $P_G/G_G$ formulas, and the $4^n$-bit hierarchical layout.

Ripple vs CLA at a glance

Aspect	Ripple-carry	Carry-lookahead
Worst-case carry delay	$O(n)$ stages	$O(\log n)$ levels (with hierarchy)
Gate count	$O(n)$	superlinear
Layout	Trivially regular	Group/level structure
When to use	Low-speed, narrow operands	Wide, high-speed datapaths

Subtraction trick

Adders also handle subtraction in 2’s complement: feed the subtrahend through XOR gates controlled by a Sub bit. When Sub = 1, the XORs invert the subtrahend, and Sub also feeds the carry-in. This computes $A+\overline{B}+1=A-B$. The reason this works: in 2’s complement, $\overline{B}+1=-B$ — flipping the bits and adding one is the negation. So $A+\overline{B}+1=A+(-B)=A-B$. One adder, two operations.