Overflow (binary arithmetic)

Overflow in binary arithmetic happens when the result of an operation can’t be represented in the same number of bits as the operands. The bits that come out are well-defined (they’re whatever the adder produced), but they don’t mean the right thing — the value has wrapped around or fallen out of range.

How to detect overflow depends on whether you’re treating the operands as unsigned or signed.

Unsigned overflow

For unsigned addition, overflow happens whenever there’s a carry out of the most significant bit. The MSB carry tells you the true sum exceeded $2^n-1$, the maximum representable.

Example, 4-bit unsigned: $1100+0101=10001$. The carry out is $1$, so the true sum ($17$) didn’t fit in 4 bits.

Hardware just checks the MSB carry-out flag.

Signed overflow (2’s complement)

For 2’s complement addition, overflow detection is different. The MSB carry no longer means “out of range” — in 2’s complement, you expect a carry out when adding two negatives, and you don’t expect one when adding two positives.

The right test: overflow occurs when the carry into the sign bit differs from the carry out of the sign bit.

Equivalently:

• Adding two positives and getting a negative → overflow.
• Adding two negatives and getting a positive → overflow.
• Adding a positive and a negative → never overflows.

The third case is intuitive: the magnitude can only shrink, so the result fits.

Example. 4-bit signed addition of $7+3$. Columns are labelled from the most significant bit (bit 3, the sign) on the left to the least significant bit (bit 0) on the right:

                bit3  bit2  bit1  bit0
Carry in:         1     1     1     0
                  0     1     1     1     (+7)
              +   0     0     1     1     (+3)
                ------------------------
Sum:              1     0     1     0
Carry out:        0     1     1     1

The carry into the sign bit (column “bit3”) is $1$; the carry out of the sign bit is $0$. They differ, so overflow happened. And indeed: the result $1010$ interpreted as 2’s complement is $-6$, not $+10$. The true answer ($+10$) couldn’t fit in 4-bit signed (range $-8$ to $+7$).

Why the two detection methods are different

The fundamental issue: in unsigned arithmetic, the MSB is a magnitude bit — losing a carry from it means losing the most significant chunk of the value. In signed arithmetic, the MSB is the sign — what matters is whether the sign of the result is consistent with the signs of the operands.

Hardware adders typically maintain both flags so the same circuit can be used for either interpretation:

• C (carry flag) — set if there’s a carry out of the MSB. Used for unsigned overflow detection and for multi-precision arithmetic (the C flag becomes the next instruction’s carry-in).
• V (overflow flag) — set if signed overflow occurred. Computed as the XOR of the two MSB carries (carry-in vs. carry-out of the sign bit).

Software then chooses which flag to check based on whether it’s working with signed or unsigned values.

Detecting both at once

The XOR-of-MSB-carries trick:

$V=C_{n-1}\oplus C_n$

where $C_{n-1}$ is the carry into the sign bit and $C_n$ is the carry out. This single XOR gate gives you signed overflow detection essentially for free in any Adder design.