Unsigned Binary Subtraction

Unsigned binary subtraction computes $M-S$ where both $M$ (minuend) and $S$ (subtrahend) are unsigned binary numbers. Two main approaches: direct subtraction with borrow propagation, or “subtraction by addition” using complements — the latter lets you reuse adder hardware.

Direct subtraction with borrows

The grade-school approach, in binary. Subtract bit by bit from least significant to most significant, borrowing from the next column when needed.

If borrowing is required at the most significant position (an “end borrow”), it means $S>M$, and the raw bit-pattern result is the 2’s complement of the true difference, with a missing minus sign.

Result interpretation

For $n$-bit unsigned subtraction:

• No end borrow → $M\ge S$. Result is correct as-is.
• End borrow → $S>M$. Result is $2^n-(S-M)$. To get the correct answer:
  1. Take the 2’s complement of the result (which gives $S-M$).
  2. Prepend a minus sign.

The "$2^n-(M-S)$" expression is exactly the 2’s complement of $M-S$ — that’s why this works.

Subtraction by addition (using 2’s complement)

Modern hardware doesn’t build a separate subtractor. Instead, it converts subtraction into addition using complements, reusing the adder circuit.

Procedure

To compute $M-S$:

1. Compute the 2’s complement of $S$.
2. Add the result to $M$.
3. Interpret:
   • If $M\ge S$: discard the carry-out from the most significant bit. Result is the correct $M-S$.
   • If $M<S$: take the 2’s complement of the result and prepend a minus sign.

Why this works

The 2’s complement of $S$ in $n$-bit arithmetic is $2^n-S$. Adding to $M$:

$M+(2^n-S)=M-S+2^n$

For $M\ge S$: the result is $M-S+2^n$. Discarding the carry out of bit $n-1$ (the $2^n$ overflow) leaves $M-S$. ✓

For $M<S$: $M-S$ is negative. The result $M-S+2^n$ is positive but represents the negative of the answer in 2’s complement. Take the 2’s complement to recover $S-M$, then negate.

Worked examples

Positive result: compute $1010100-1000011$.

Take 2’s complement of $1000011$: invert → $0111100$, add 1 → $0111101$.

Add: $1010100+0111101=10010001$.

Discard the end carry (bit 7): $0010001$. Result: $0010001=17$. ✓ (Check: $84-67=17$.)

Negative result: compute $1000011-1010100$.

Take 2’s complement of $1010100$: invert → $0101011$, add 1 → $0101100$.

Add: $1000011+0101100=1101111$.

No end carry (bit 7 is part of the result). Take 2’s complement of $1101111$: invert → $0010000$, add 1 → $0010001$. Prepend minus: $-0010001=-17$. ✓

Subtraction by addition using 1’s complement

Slightly different procedure. Add the 1’s complement of $S$ (just bit-inverted, no $+1$). If there’s a carry-out, perform an end-around carry — add the carry back to the result. If no carry-out, take the 1’s complement of the result and add a minus sign.

This is the older method, used in early computers. 2’s complement won out because it doesn’t need the end-around-carry step. See 1’s Complement and Radix Complement.

Why subtraction by addition

Hardware-economy reason: an adder is a complex circuit. Building a separate subtractor would double the silicon. Adding a row of XOR gates to optionally invert one operand (controlled by a “Sub” bit) lets one adder do both operations.

When Sub = 0: the XORs pass $S$ unchanged, $C_{\text{in}}=0$, the adder computes $M+S$.

When Sub = 1: the XORs invert $S$, $C_{\text{in}}=1$, the adder computes $M+\overline{S}+1=M+(-S)=M-S$.

This adder/subtractor design is standard in CPUs. See 2’s Complement Arithmetic for the full picture.

For unsigned numbers and arithmetic, see Binary number system. For signed representations, see Signed binary number.