BJT saturation mode

Saturation mode is the BJT region where both junctions are forward-biased. The transistor is “on hard”: fully turned on, $V_{CE}$ collapses to a small value, and the collector current is set by whatever the external circuit can supply — not by $\beta i_B$. It is the BJT’s closed-switch state in digital logic.

Naming warning. “Saturation” means the opposite thing for a BJT than for a MOSFET. MOSFET saturation is the amplifying region; BJT saturation is the on-hard, fully-conducting region. The MOSFET region that corresponds to BJT saturation is the triode region. Keep the BJT operating modes map straight or this will bite you.

What happens physically

Start in active mode and keep driving the base harder. Active mode wants $i_C=\beta i_B$, so more base current demands more collector current. But the collector current has to flow through the external collector circuit (typically $R_C$ to $V_{CC}$), and each extra milliamp drops more voltage across $R_C$, pulling the collector voltage down toward the emitter. Eventually $V_{CE}$ gets so small that the collector–base junction also becomes forward-biased. At that point you have left active mode: both EBJ and CBJ are forward-biased, and that is saturation.

Operation of the npn BJT in saturation: both junctions forward-biased, $V_{CE}$ small (about 0.2 V), and $i_C$ set by the external circuit, not by $\beta i_B$.

$V_{CE(sat)}$ and the model

In saturation $V_{CE}$ is pinned to a small, roughly-constant value called $V_{CE(\text{sat})}$, typically 0.1–0.3 V (a representative number is 0.2 V). The base–emitter still looks like a forward diode, so $V_{BE}\approx 0.7\text{V}$ as in active mode. The simplified large-signal model in saturation is therefore: a fixed 0.7 V from base to emitter, and a fixed $V_{CE(\text{sat})}\approx 0.2\text{V}$ from collector to emitter. The full diode-pair picture has both junctions forward; the edge of saturation (the boundary with active mode) is where the CBJ just starts to conduct, around $V_{BC}\approx 0.4\text{V}$.

Saturation large-signal model: fixed $V_{BE}\approx 0.7\text{V}$ (same as active) and fixed $V_{CE(\text{sat})}\approx 0.2\text{V}$ across collector–emitter; the edge of saturation sits at $V_{BC}\approx 0.4\text{V}$.

The relation $i_C=\beta i_B$ does NOT hold here

This is the single most common way students wreck a BJT problem. In saturation the extra base current you push in does not produce proportionally more collector current — the collector current is whatever the external circuit allows, and the surplus base current simply “spills over” into recombination without showing up at the collector. Define ${\beta }_{\text{forced}}=I_C/I_B$ in saturation; it is much smaller than the device’s actual $\beta$.

Because of this, the workflow is always: assume active, solve, then check. If the active-mode solution predicts $V_{CE}$ below about 0.3 V (or worse, negative), the active assumption is false and the device is actually in saturation. You then redo the analysis using $V_{CE}=V_{CE(\text{sat})}=0.2\text{V}$ as the known quantity and let $I_C$ fall out of the external circuit instead. A full worked saturation-check failure is in BJT DC analysis.

As a switch, saturation is the “closed” state (small voltage drop, current limited by the load) and cut-off is the “open” state.