Source degeneration

Source degeneration is adding an un-bypassed resistor $R_S$ in the source path of a Common-source amplifier. It introduces local Negative feedback that trades away gain for predictability, linearity, and bandwidth — usually a very good trade.

The feedback mechanism

Picture the signal increasing $v_{gs}$. That raises the drain current $i_d$. But $i_d$ also flows through $R_S$, so the source voltage rises by $i_d{R}_S$. The gate-source voltage is gate minus source, so a rising source eats into the effective $v_{gs}$. The device’s own response (more current) pushes back against the input that caused it — that is negative feedback, applied locally at one transistor.

Gain with degeneration

Working through the MOSFET small-signal model, the effective gate-source voltage is the input minus $i_d{R}_S$, and $i_d=g_m{v}_{gs,\text{eff}}$. Solving:

$A_v=-\frac{g_m{R}_D}{1+g_m{R}_S}$

where $g_m$ is the MOSFET transconductance, $R_D$ the drain resistor, and $R_S$ the source resistor. The bare common-source gain $-g_m{R}_D$ is divided by the feedback factor $(1+g_m{R}_S)$. Larger $R_S$ ⇒ more feedback ⇒ less gain.

$R_S$ adds negative feedback; gain ÷$(1+g_m{R}_S)$ but more predictable and linear.

Why give up gain on purpose

The payoff is in the strong-feedback limit. When $g_m{R}_S\gg 1$:

$A_v\approx -\frac{g_m{R}_D}{g_m{R}_S}=-\frac{R_D}{R_S}$

The gain now depends only on a resistor ratio — not on $g_m$, not on $V_t$, not on $k_n$, none of the process-dependent, temperature-sensitive transistor parameters. Two “identical” transistors that would give wildly different bare gains now give the same predictable $-R_D/R_S$. That robustness is the entire point. Degeneration also linearises the stage (the feedback compresses the nonlinear square-law curve) and improves bandwidth. The cost — lower raw gain — is exactly the “excess gain” a bare common-source had no good use for anyway.

This is the MOSFET counterpart of Emitter degeneration in a BJT (an un-bypassed emitter resistor doing the same job). When you want the DC bias benefit of $R_S$ but not the AC gain loss, put a Bypass capacitor across $R_S$: it shorts $R_S$ for AC (full gain restored) while leaving it for DC (MOSFET biasing stability intact). It also raises the stage’s input resistance.