Step response on transmission line

When a DC voltage is suddenly applied to a Transmission line (e.g., switching on a power supply, or driving a digital logic transition), the line doesn’t reach steady state instantly. A wavefront propagates from source to load, reflects, returns, reflects again — a multi-bounce transient that gradually settles.

Setup

A line of length $l$, characteristic impedance $Z_0$, propagation velocity $u_p$. Switched on at $t=0$, connected to a DC source $V_g$ with internal impedance $R_g$ and load $R_L$.

One-way travel time:

$T=\frac{l}{u_p}.$

This is the time for a wavefront to traverse the line once.

Phase 1: Initial launch ($t=0$)

At the instant the switch closes, the line looks like its characteristic impedance to the source — not like the load yet, since no wave has reached the load. The source sees a voltage divider between $R_g$ and $Z_0$, and the initial forward wave has amplitude:

$V_1^{+}=\frac{V_g\cdot Z_0}{R_g+Z_0}.$

This wave propagates in $+\hat{\mathbf{z}}$ at speed $u_p$.

Phase 2: First reflection ($t=T$)

When the wavefront reaches the load at $t=T$, the load enforces $V_L=I_L{R}_L$. If $R_L\ne Z_0$, the incoming wave can’t match this — a reflection $V_1^{-}$ is generated:

$V_1^{-}={\Gamma }_L{V}_1^{+},{\Gamma }_L=\frac{R_L-Z_0}{R_L+Z_0}.$

The voltage at the load at $t=T^{+}$ is the sum of incident plus reflected:

$V_L=V_1^{+}(1+{\Gamma }_L).$

Phase 3: Second reflection ($t=2T$)

The reflected wave returns to the source at $t=2T$. If $R_g\ne Z_0$, it also fails to match — a new forward wave $V_2^{+}$ is generated:

$V_2^{+}={\Gamma }_g{V}_1^{-}={\Gamma }_g{\Gamma }_L{V}_1^{+},{\Gamma }_g=\frac{R_g-Z_0}{R_g+Z_0}.$

This is the start of “bouncing back and forth,” with each round trip multiplying the amplitude by ${\Gamma }_g{\Gamma }_L$.

Long-time steady state

After many round trips, the geometric series of bounces converges:

$V_{\text{steady}}(z)=V_1^{+}(1+{\Gamma }_L){\sum }_{n=0}^{\infty }({\Gamma }_g{\Gamma }_L{)}^n=\frac{V_1^{+}(1+{\Gamma }_L)}{1-{\Gamma }_g{\Gamma }_L}.$

Substituting $V_1^{+}=V_g{Z}_0/(R_g+Z_0)$ and simplifying with the definitions of ${\Gamma }_g,{\Gamma }_L$:

$V_{\text{steady}}(z)=\frac{V_g{R}_L}{R_g+R_L}.$

The transient settles to the DC resistive-divider answer — what you’d predict from lumped circuit theory, ignoring the line entirely. The transmission line is “invisible” at DC steady state (lossless case).

The transient is the price you pay during the settling time of order $\sim 1/(1-{\Gamma }_g{\Gamma }_L)\cdot T$ — a few round trips for moderate mismatches, many round trips for severe ones.

Three special terminations

Matched load ($R_L=Z_0$, ${\Gamma }_L=0$): No reflection at the load. The forward wave is absorbed; voltage steps up to $V_g{Z}_0/(R_g+Z_0)$ and stays there. Cleanest possible response — one step, no ringing. The reason RF designers obsess over matching.

Open load ($R_L=\infty$, ${\Gamma }_L=+1$): The wave reflects fully in phase. Voltage at the open end doubles. If the source is also mismatched (${\Gamma }_g\ne 0$), the wave bounces back and the voltage oscillates around the steady-state value, decaying geometrically.

Short load ($R_L=0$, ${\Gamma }_L=-1$): The wave reflects fully inverted. Voltage at the short stays zero, current doubles. Bouncing creates the dual of the open-circuit oscillation pattern.

Why a digital signal “rings”

In high-speed digital design, the source and load are not perfectly matched. A 0→1 transition launches a wave that bounces a few times before settling. If ${\Gamma }_g{\Gamma }_L>0$, the bounces produce overshoot and undershoot (“ringing”) — the voltage at the receiver oscillates around the final value.

For very fast edges (short rise time relative to $T$), this ringing can cross logic thresholds multiple times, causing false transitions. Mitigation strategies:

1. Source-series termination: add $R_g=Z_0$ at the driver. ${\Gamma }_g=0$ kills back-reflections, so any waveform that arrives at the source is absorbed. The first reflection from the load eventually settles things out.
2. Parallel termination at the load: add a resistor in parallel at the load so the load impedance matches $Z_0$. ${\Gamma }_L=0$. Cleanest response but consumes DC power (the resistor draws current at logic-high).
3. Differential signaling and controlled-impedance PCBs: the modern approach for multi-Gbps interconnects.

This is also why high-speed PCB design specifies things like “50 Ω microstrip” — you’re designing the line to match the components, so transient ringing is controlled by design rather than after the fact.

Computing the response

Two equivalent ways:

• Bounce diagram: graphical, intuitive. Locate $(z,t)$ on the diagram, sum amplitudes of waves that have passed.
• Closed-form sum: $v(z,t)=\sum$ of bounces explicit through time $t$. For each round trip, add $V_n^{\pm }{e}^{j(\omega t-\beta z)}$ if applicable.

For complex problems, time-domain SPICE simulation handles the bounces automatically.