Setup time, hold time, and clock frequency

A flip-flop has timing constraints that determine the maximum clock frequency it can run at. Three numbers matter:

• $t_{su}$ (setup time) — how long the data input must be stable before the clock edge.
• $t_h$ (hold time) — how long the data must remain stable after the clock edge.
• $t_{cQ}$ (clock-to-Q delay) — how long after the clock edge before the new $Q$ value is valid at the output.

If any of these is violated, the flip-flop may go metastable — its output settles to an unpredictable value (sometimes neither $0$ nor $1$, oscillating for a while). Metastability is the chief enemy of synchronous design.

Why each matters

• $t_{su}$ ensures the data input is held stable long enough before the clock edge that the flip-flop’s internal cross-coupled feedback loop can be driven decisively into one of its two stable states (the $Q=0$ basin or the $Q=1$ basin) before the edge latches the value. Set up too late → the loop is still being pushed by the new input when the edge arrives, leaving it near its unstable equilibrium → metastability.
• $t_h$ ensures the input doesn’t change during the capture window. Held too short → the loop gets pushed back across its threshold before it has fully committed → metastability.
• $t_{cQ}$ is just propagation delay — once the edge arrives, the new $Q$ value isn’t instantly visible at the output.

The “RC charging” picture is a useful first sketch but doesn’t capture metastability. The deeper reason these constraints exist is the bistable feedback loop: like a ball balanced on a knife-edge, it needs a clear push and time to roll into one of the two basins. Bumping it just as the edge arrives can leave it teetering on the edge for an arbitrarily long time before it finally falls one way or the other.

Maximum clock frequency

In a synchronous circuit, after one flip-flop fires, the new $Q$ value has to propagate through some combinational logic and arrive at the next flip-flop’s $D$ input before that flip-flop’s setup time. The minimum clock period $T_{\min }$ is therefore:

$T_{\min }=t_{cQ}+t_{logic}+t_{su}$

where $t_{logic}$ is the worst-case combinational delay between the source flip-flop’s $Q$ and the destination flip-flop’s $D$.

The maximum frequency is just the inverse:

$F_{\max }=\frac{1}{T_{\min }}$

Worked example

Given $t_{su}=0.6\text{ns}$, $t_h=0.4\text{ns}$, $0.8\le t_{cQ}\le 1.0\text{ns}$, and a per-gate delay of $1+0.1k$ ns where $k$ is the number of inputs to the gate.

Assume the data path between two flip-flops contains a single 1-input NOT gate (gate delay = $1+0.1\cdot 1=1.1\text{ns}$).

$T_{\min }=t_{cQ}^{\max }+t_{NOT}+t_{su}=1.0+1.1+0.6=2.7\text{ns}$

$F_{\max }=\frac{1}{2.7\text{ns}}\approx 370\text{ MHz}$

You use the maximum $t_{cQ}$ for $T_{\min }$ because timing analysis must hold for the worst case.

Hold-time check

The hold-time check uses the minimum delays. The destination flip-flop’s $D$ must not change for $t_h$ after the clock edge. The fastest path from source $Q$ to destination $D$ is $t_{cQ}^{\min }+t_{logic}^{\min }$.

$t_{cQ}^{\min }+t_{logic}^{\min }>t_h$

For the same example: $0.8+1.1=1.9\text{ns}>0.4\text{ns}$. ✓ Hold time is satisfied.

If hold time fails, the new $Q$ propagates through too quickly — the destination flip-flop sees the new value during its hold window instead of holding the old value. The fix is to insert delay (extra buffers in the path) or, in serious cases, redesign to spread out the timing.

Choosing a flip-flop

For new designs:

• Gated SR latch. Don’t use directly; it’s a building block for other flip-flops.
• D flip-flop. The default. Simplest semantics, smallest CMOS footprint, native to FPGAs.
• T flip-flop. Niche use for counters; usually built as D + XOR.
• JK flip-flop. Versatile but more wiring than D; rarely chosen unless legacy design.

Asynchronous Clear and Preset inputs are highly desirable on whatever flip-flop you pick — without them, the circuit’s reset behavior is unpredictable.