Multiple-output circuit

A multiple-output circuit computes more than one Boolean function from the same set of inputs. When two outputs share product terms, you can reduce total cost by sharing the gates that produce those terms instead of duplicating them.

The key insight: if both $f_1$ and $f_2$ use the term $x_1{x}_3$, build one AND gate for $x_1{x}_3$ and feed its output into both $f_1$‘s and $f_2$‘s OR gates. You’ve saved a gate.

Example

Two functions:

$f_1=\overline{x_1}\overline{x_3}+x_1\overline{x_3}+x_2\overline{x_3}{x}_4$

$f_2=\overline{x_1}\overline{x_3}+x_1\overline{x_3}+x_2{x}_3{x}_4$

Each function has GIC of $14$ on its own. Built as two completely separate circuits, total is $28$.

But the first two terms ($\overline{x_1}\overline{x_3}$ and $x_1\overline{x_3}$) appear in both. If you build them once and feed both ORs, you save $8$ inputs:

Combined cost is $22$ — a $6$-input savings, achieved by sharing the two common ANDs and their literals.

When sharing pays

Sharing is worthwhile when the same product term appears in multiple outputs and the cost of an extra wire (running the shared term to multiple ORs) is less than the cost of duplicating the gates. In practice this is almost always true.

To find sharing opportunities systematically: do a Karnaugh Map for each output, and look for groups that show up in more than one map. Tools like Espresso do this automatically when minimizing multi-output Boolean functions.

This generalizes beyond SOP. The same logic applies to Multilevel synthesis — once you’ve factored an expression into intermediate signals, those intermediates can be shared by other outputs that use the same factor.

A PLA takes advantage of multi-output sharing structurally: its AND plane produces a fixed set of product terms, and its OR plane lets every output draw on any subset of those terms. That’s exactly what makes a PLA more area-efficient than $n$ separate two-level circuits when the outputs overlap in their product terms.