VHDL architecture

A VHDL architecture is the implementation paired with a VHDL entity — the “how” that complements the entity’s “what.” An architecture describes the logic that produces the entity’s outputs from its inputs.

architecture LogicFunc of example2 is
begin
    f <= (x1 AND x3) OR (x2 AND x4);
    g <= (x1 OR NOT x3) AND (NOT x2 OR x4);
end architecture LogicFunc;

The architecture has a name (LogicFunc), an entity it implements (of example2), an optional declarative section (between is and begin for internal signals, components, types), and a body containing the actual logic.

Three styles

VHDL allows three architectural styles, often mixed within one architecture:

Dataflow

Concurrent signal assignments:

architecture dataflow of mux2to1 is
begin
    f <= (s AND b) OR (NOT s AND a);
end architecture;

Each <= assignment runs continuously, like a wire fed by gates. Multiple assignments execute in parallel — there’s no order. This matches what hardware actually does.

Behavioural

Process-based, sequential-feeling code:

architecture behavioural of mux2to1 is
begin
    process(s, a, b)
    begin
        if s = '1' then
            f <= b;
        else
            f <= a;
        end if;
    end process;
end architecture;

Inside a process, statements execute in sequence (one by one). The process re-runs whenever a signal in its sensitivity list changes. Useful for clocked logic and complex control structures.

Structural

Wiring up sub-components:

architecture structural of full_adder is
    component half_adder
        port (a, b : in std_logic;
              s, c : out std_logic);
    end component;
    signal s1, c1, c2 : std_logic;
begin
    HA1: half_adder port map (a => a,  b => b,   s => s1,  c => c1);
    HA2: half_adder port map (a => s1, b => cin, s => sum, c => c2);
    cout <= c1 or c2;
end architecture;

Instances of sub-components are wired together by signals. Mirrors how hardware engineers actually compose larger designs from smaller blocks.

The example uses named association (port_name => signal) rather than positional. Positional association — port map (a, b, s1, c1) — depends on remembering the exact port order from the component declaration; reorder the component’s ports later and every instantiation silently rewires to the wrong signals. Named association is verbose but robust, and is strongly preferred in modern VHDL.

Internal signals

If you need a temporary value used in multiple places, declare a signal between is and begin:

architecture LogicFunc of Q1 is
    signal k : std_logic;
begin
    k <= x1 AND x2;
    f <= k AND NOT x1;
end architecture LogicFunc;

Signals act like internal wires. They have a type and (optionally) an initial value. They’re not strictly necessary — you can write longer expressions inline — but they help readability when an intermediate value is reused.

Multiple architectures per entity

A single entity can have multiple architectures, each implementing the interface differently:

architecture rtl of counter is
    -- synthesizable RTL implementation
end architecture rtl;
 
architecture behavioural of counter is
    -- abstract simulation model
end architecture behavioural;

You select which one to use during compilation. Common pattern: one fast-but-abstract version for early simulation, one synthesizable version for actual hardware.

Why concurrent assignments

The signal assignments in dataflow style are concurrent — they all execute simultaneously, modeling actual hardware where every gate evaluates in parallel. There’s no notion of “this line runs before that one” in a dataflow architecture.

This is why VHDL is a hardware description language, not a programming language. The text describes parallel circuits, not a sequence of CPU instructions.

For the interface side that an architecture implements, see VHDL entity. For the assignment operator and how signals work, see VHDL signal assignment. For the broader language, see VHDL.