Logic voltage levels and noise margin

A digital signal isn’t just $0$ or $1$ — it’s a voltage that’s interpreted as $0$ or $1$. The convention is positive logic: $0$ is a low voltage (near ground) and $1$ is a high voltage (near $V_{DD}$). The noise margin is the buffer between the worst-case voltage a gate guarantees as output and the worst-case voltage the next gate is willing to accept as input.

Two key margins:

• High-state noise margin $N{M}_H=V_{OH(\min )}-V_{IH(\min )}$
• Low-state noise margin $N{M}_L=V_{IL(\max )}-V_{OL(\max )}$

The four voltages above each name a guarantee from the gate’s data sheet:

• $V_{OH(\min )}$ — minimum voltage the driving gate will produce when outputting $1$.
• $V_{IH(\min )}$ — minimum voltage the receiving gate is guaranteed to interpret as $1$.
• $V_{OL(\max )}$ — maximum voltage the driving gate will produce when outputting $0$.
• $V_{IL(\max )}$ — maximum voltage the receiving gate is guaranteed to interpret as $0$.

Why margins matter

Real signals don’t arrive at the next gate as clean square waves. Wires couple capacitively to neighbors (crosstalk), the supply voltage dips when other parts of the chip switch, and ground bounces. All of that injects noise onto the signal between gates.

If your driver guarantees $V_{OH(\min )}=4.4\text{V}$ on a $V_{DD}=5\text{V}$ supply, and the receiver only needs $V_{IH(\min )}=3.5\text{V}$ to recognize $1$, you have $0.9\text{V}$ of headroom — the noise margin $N{M}_H$. Noise has to push the signal more than $0.9\text{V}$ down before the receiver risks misreading it as $0$. Note that you compute the margin from $V_{OH(\min )}$, not from $V_{DD}$: a gate’s actual output high voltage is normally a bit below the supply rail (because of saturation drops or pull-up impedance), so using $V_{DD}$ would over-estimate the margin. Always pull the four voltages from the data sheet rather than assuming $V_{OH}=V_{DD}$.

A gate with a small noise margin is fragile — you’ll see spurious bit flips and intermittent failures. A gate with a large noise margin is robust but typically slower or more power-hungry. CMOS happens to give large noise margins (close to $V_{DD}/2$ on each side) at low static power, which is one of the main reasons it dominates digital design.

The reference voltages: $V_{DD}$ is the positive supply, $V_{SS}$ is the lowest voltage (usually ground). Output values cluster near $V_{DD}$ for a $1$ and near $V_{SS}$ for a $0$, with the input thresholds set comfortably between.